As integrated circuit scaling proceeds into the deep sub-micron regime, the number of transistors on high performance, high density ICs is in the tens of millions, in accordance with the historical trend of Moore's Law. This has necessitated that such ICs feature multiple layers of high-density metal interconnects, and that the layers be separated by inter level dielectrics (ILD), also sometimes known as inter-metal dielectrics (IMD). The parasitic capacitance associated with these metal interconnections has become a major factor that limits the circuit speed of such high performance ICs. A conventional ILD (also known as regular-k dielectric) typically has a dielectric constant (also known as k value) of about 3.8 to about 8.0. However, the relatively high-k value of the regular-k dielectrics results in high parasitic capacitance. Recently, low-k dielectrics such as CVD black diamond (a trademark of Applied Materials), which has a k value of about 3.0, have been widely used by the semiconductor industry to reduce the parasitic capacitance between the metal lines, hence improving circuit performance. The k value of SiO2 (about 3.8 to 4.2) is typically used as the dividing line between a low-k and a regular-k.
However, low-k materials cannot be used as the first level dielectric since their physical and chemical properties are significantly different from the regular-k materials. For example, low-k materials typically have high leakage current, low breakdown voltage, bad adhesion to caps and liners, and low thermal stability, so that using a low-k material close to the devices may degrade performance.
To solve the parasitic capacitance problem, a composite structure consisting of two layers is frequently used. The layer close to the devices is formed of regular-k materials, and the layer away from the devices is formed of low-k materials. This effectively lowers the parasitic capacitance. However, a new problem is introduced. In a metal structure comprising a regular-k dielectric, in which tungsten (including a conductor liner/barrier such as titanium nitride) is typically used as contact plugs and a thick low-k dielectric, the adhesion between the thick regular-k dielectric and the thick low-k dielectric is not stable. This will lead to film delamination and in turn cause low chip yield.